As process technology scales down to below 30 nm, it becomes challenging to develop memory devices (e.g., flash memories) with a smaller geometry due to worsening transistor reliability and characteristics such as retention and endurance. Moreover, the cost for developing every next generation of process technology increases enormously. Against this background of factors, through-silicon-via (TSV) technology reveals itself as a good candidate to overcome scaling limits, and increase memory capacity without diminishing performance or increasing costs. Fundamentally, TSV technology involves methods for using short vertical interconnects through stacked dies, thereby implementing semiconductor devices with a 3-dimensional structure. TSV technology may thus provide significant benefits including high density, high bandwidth, low power consumption and small form factor.
The following publications provide additional background material related to TSV technology and are hereby incorporated by reference herein:    J. Burns, et al., “Three-Dimensional Integrated Circuits for Low Power, High-Bandwidth System on a Chip,” ISSCC Dig. Tech. Paper, pp. 268-269, February 2001.    P. E. Emma, E. Kursun, “Is 3D chip technology the next growth engine for performance improvement?” IBM J. Res. & Dev. 52, No. 6, 541-552, November 2008.    Gabriel H. Loh, “3D-Stacked Memory Architectures for Multi-Core Processors,” 35th ACM/IEEE International Conference on Computer Architecture, June 2008.    R. Patti, “Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs,” Proc. of the IEEE, vol. 84, no. 6, June 2006.    W. Topol, J. D. C. La Tulipe, L. Shi, et al., “Three Dimensional Integrated Circuits,” IBM Journal of Research and Development, vol. 50, no. 4/5, pp. 491-506, July/September 2006.    Uksong Kang, et al., “8 Gb 3D DDR3 DRAM Using Through-Silicon-Via Technology,” ISSCC Dig. Tech. Paper, pp. 130-131, February 2009.
Two main types of TSV technology are “Via First” and “Via Last”. Depending on the type of TSV technology, either reactive-ion etching (RIE) or laser drilling is performed before a TSV metallization process (TSV formation). TSV implementation using RIE and Via First has been discussed in M. Kawano, et al., “A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer,” IEEE IEDM Dig. Tech. Papers, pp. 581-584, 2006, hereby incorporated by reference herein. Additionally, TSV implementation using laser drilling and Via Last has been discussed in Uksong Kang, et al., “8 Gb 3D DDR3 DRAM Using Through-Silicon-Via Technology,” ISSCC Dig. Tech. Paper, pp. 130-131, February 2009.